The present invention relates to a semiconductor device and a method for manufacturing the same and a semiconductor memory device and a method for manufacturing the same and, more specifically, to a DRAM (dynamic random access memory) including a semiconductor device having a wiring structure adopting a borderless contact technique and a stacked capacitor.
Semiconductor devices have recently been miniaturized in accordance with progress in semiconductor process technique and dramatically improved in degree of integration.
In a prior art semiconductor device having a structure of connecting wiring layers through a contact via, the wiring layers are increased in width at the contact portion since there are variations in pattern alignment in the lithographic process, measurements, and etching depths of contact holes. The increase in width of the wiring layers necessitates a margin for alignment, which makes the chip area larger and hinders the device from being miniaturized. Therefore, a borderless contact technique not requiring the alignment margin, has recently been used widely in which an interlayer insulation film between upper and lower wirings is flattened completely using a polishing technique such as CMP (chemical mechanical polishing) to uniform an amount of etching of the insulation film.
FIG. 1 is a cross-sectional view illustrating the major part of a typical prior art semiconductor device constituted by the borderless contact technique described above.
In the prior art semiconductor device, for example, an element isolation insulation film 102, which is a silicon oxide film, is selectively buried in a surface portion of a p-type silicon substrate 101 to form an element isolation region 101a. In this region 101a, a gate electrode 103A is provided on the silicon substrate 101. In an element region 101b other than the region 101a, a gate electrode 103B is formed on the substrate 101 with a gate oxide film 104 interposed therebetween. The gate electrodes 103A and 103B each have a layered structure of polysilicon 103a and tungsten silicide 103b. An on-gate insulation film 105, which is a silicon nitride film, is formed on the upper surface of each of the gate electrodes 103a and 103b, and a gate side-wall insulation film 106, which is also a silicon nitride film, is formed on the side-wall thereof.
Furthermore, shallow n-type diffusion layers 107a and 107b serving as source and drain regions, are formed in the surface portion of the silicon substrate 101 in the element region 101b, using the gate electrode 103B as a mask.
A plug portion 109A connecting with the gate electrode 103A and a contact portion 109B connecting with one of the diffusion layers 107a and 107b are provided in a first interlayer insulation film 108 formed all over the surface of the substrate 101 including the surfaces of the gate electrodes 103A and 103B. Each of the portions 109A and 109B is so constituted that a contact hole 108a is formed in the first interlayer insulation film 108, a barrier metal layer 109a of Ti/TiN is formed at least on the bottom and side of the hole 108a, and a metal layer 109b of tungsten or aluminum is formed on the layer 109a.
A second interlayer insulation film 110 is formed all over the surface of the first interlayer insulation film 108, including the surfaces of the plug portion 109A and contact portion 109B, and both a plug portion 111A connecting with the plug portion 109A and a wiring layer 111B connecting with the contact portion 109B are formed on the film 110. Each of the plug portion 111A and wiring layer 111B is so constituted that both a contact hole 110a and a trench 110b are formed in the second interlayer insulation film 110, a barrier metal layer 111a of Ti/TiN is formed on at least the bottom and side of each of the hole 110a and trench 110b, and a metal layer 111b of tungsten or aluminum is formed on the layer 111a.
In the semiconductor device so constituted, for example, when the second interlayer insulation film 110 is processed selectively by RIE (reactive ion etching) to form the above contact hole 110a and trench 110b, an amount of etching for the RIE is set larger in consideration of variations in pattern alignment in the lithographic process, measurements, thickness of the second interlayer insulation film 110, etc. For this reason, when the film 110 is processed, that part of the first interlayer insulation film 108 which contacts the plug and contact portions 109A and 109B, is over-etched to obtain recesses. 112a and 112b. Usually these recesses have various measurements since they are influenced complexly and randomly by the above-described variations.
The recess 112b having a large area may not cause a serious problem, whereas the recess 112a having a very small area has a drawback in which the barrier metal layer 111a and metal layer 111b are formed incompletely to cause a void, and a conductive film cannot be covered sufficiently. The drawback will be disadvantageous to suppressing an increase in contact resistance, a variation, and a decrease in wiring reliability. Further, the drawback is not limited to the formation of the plug portion 111A and wiring layer 111B, but is true of the formation of the contact via for connecting the upper and lower wiring layers and that of a storage electrode in a DRAM using a stacked capacitor.
For example, in the layout of cells of the DRAM, the borderless contact technique has been employed in order to reduce the chip area. Even though the area per bit is decreased in accordance with miniaturization of the DRAM, several tens of femto-farads (fF) of the storage capacitance of the capacitor have to be secured. For this reason, a three-dimensional structure such as a stacked structure and a trenched structure, is adopted in the capacitor of the DRAM which is progressing in miniaturization.
It is considered to employ not only a silicon oxide film and a silicon nitride film, but also a high dielectric thin film, such as tantalum pentaoxide (Ta.sub.2 O.sub.5), strontium titanic acid (SrTiO.sub.3 (STO)), strontium barium titanic acid ((Ba, Sr) TiO.sub.3 (BSTO)), as the capacitor insulation film.
In order to apply the high dielectric thin film to a highly-integrated semiconductor device appearing after a 1-Gbit DRAM, in which the high dielectric thin film is formed by the minimum processing measurements of 0.2.mu.m or less, the thin film has to be formed uniformly and at high grade on a storage electrode. Thus, the advantage of the storage electrode, to which a complicated processing of forming a fin type storage electrode and making the surface of the electrode coarse is applied, will be lost. The high dielectric thin film is thin in comparison with the oxide film, but its actual thickness is relatively large, which will not take effect too much.
In particular, when the storage electrode has a complicated shape, the leak current of the capacitor increases, the breakdown voltage thereof lowers, and the reliability thereof deteriorates. It is thus desirable to form a storage electrode having a simple shape when a high dielectric thin film is employed in the capacitor insulation film.
FIG. 2 is a cross-sectional view illustrating the structure of a prior art DRAM cell using a simple, stacked capacitor.
For example, an element isolation trench portion 202 is formed selectively in a surface portion of an p-type silicon substrate 201, and n-type diffusion layers 204 serving as source and drain regions are formed therein using a gate electrode 203 as a mask, thus obtaining a plurality of MOS transistors. The gate electrode 203 is constituted of polysilicon and tungsten silicide and formed on the silicon substrate 201, with a gate oxide film 205 interposed therebetween. The top and side of the gate electrode 203 are covered with an insulation film 206.
A bit line 207 formed of both polysilicon and tungsten is connected to one of the diffusion layers 204 of the source and drain regions. An interlayer insulation film 208 is formed on the entire surface of the substrate 201 including the surface of the bit line 207, and a plug portion 209 connecting with the other diffusion layer 204, is provided in the interlayer insulation film 208. Furthermore, an interlayer insulation film 301 is deposited on the layer 208 to form a storage electrode 210 connecting with the plug portion 209 and provide a plate electrode 212 with a capacitor insulation film 211 interposed therebetween. In this case, if an Ru film is used as-both the storage electrode 210 and plate electrode 212 and a BSTO film is employed as the capacitor insulation film 211, the structure of a stacked capacitor can be simplified.
To form the interlayer insulation film 301 on the interlayer insulation film 208 prevents the plug portion 209 from being exposed after the storage electrode 210 is formed, the exposure of the plug portion 209 being caused due to variations in pattern alignment in the lithographic process and in measurements, when the short side of the storage electrode 210 is almost equal to the width of the plug portion 209. In other words, if the BSTO film is formed with the plug portion 209 exposed from the surface, a capacitor is to be formed between the storage electrode 210 and plug portion 209 the matter of which differs from that of the storage electrode 210. This capacitor increases in leak current, decreases in breakdown voltage, and degrades in reliability.
In order to prevent a capacitor from being formed between the capacitor insulation film 211 and plug portion 209, the interlayer insulation film 301 is deposited further on the interlayer insulation film 208 including the surface of the plug portion 209, a trench 302 is formed in that area of the film 301 where the capacitor is to be formed, and the storage electrode 210 is formed in the trench 302 and connected to the plug portion 209 at the bottom of the trench 302.
However, the capacitor having the above constitution has to be formed by setting the short side of each of the plug portion 209 and trench 302 to the minimum. Due to both a variation in pattern alignment in the lithographic process and over-etching in the region where the capacitor is to be formed, not only the interlayer insulation film 301 on the plug portion 209, but also part of the interlayer insulation film 208 is etched to excess, and a recess 303 is formed alongside the plug portion 209. The recess 303 varies in size and aspect ratio because of variations in pattern alignment and an amount of over-etching.
If, in particular, the recess 303 is very small, the storage electrode 210 is formed incompletely therein; therefore, neither the capacitor insulation film 211 nor the plate electrode 212 formed on the storage electrode 210 is sufficiently covered with an Ru film. Such a capacitor increases in leak current and thus decreases in reliability.